Method and apparatus for mobility enhancement in a semiconductor device

ABSTRACT

A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region ( 18 ) is formed over a substrate that is bi-axially stressed. Source ( 30 ) and drain ( 32 ) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.

FIELD OF THE INVENTION

This invention relates to semiconductor devices, and more particularly,to semiconductor devices that have enhanced mobility.

RELATED ART

In the manufacture of semiconductor devices, silicon has been by far themost popular choice for the semiconductor material. Transistorperformance has been enhanced regularly through a variety of processimprovements. One of the improvements has been to alter the stress inthe silicon in order to improve mobility. Some of the techniques haveincluded using other materials in addition to the silicon to bring aboutthe stress and the consequent mobility improvement. For example, asilicon layer that has germanium added results in a silicon germaniumlayer that is under compressive stress. Such a silicon germanium layerunder compressive stress is useful in improving the mobility of thecarriers for a P channel transistor. Finding ways to create tensilestress is for improving the carriers for an N channel transistor.

A variety of techniques have been developed for achieving both tensileand compressive stresses. The mobility improves with increases in stressbut ultimately, enough increase in stress causes fractures in thecrystal lattice, which renders it useless for semiconductormanufacturing. Another issue is that a typical stress enhancingtechnique is useful in improving mobility in only one of either shortchannel or long channel transistors. For example, the typical problemwith a bi-axial stress is that it does little to improve the mobility ofcarriers in a short channel transistor. On the other hand, the typicalproblem with a uni-axial stress is that it does little to improvemobility of carriers in a long channel transistor. Thus, the mobilityenhancements cause changes in mobility with changes in channel length,which makes it more difficult to provide models for the transistors,which in turn makes it more difficult to design circuits usingtransistors with these mobility enhancements.

Thus, there is a need to provide mobility enhancements that improve onone or more of the problems noted above.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitedby the accompanying figures, in which like references indicate similarelements, and in which:

FIG. 1 is a cross section of a semiconductor structure at a first stagein processing according to a first embodiment of the invention;

FIG. 2 is a cross section of the semiconductor structure of FIG. 1 at asubsequent stage in processing;

FIG. 3 is a cross section of the semiconductor structure of FIG. 2 at asubsequent stage in processing;

FIG. 4 is a cross section of a semiconductor structure at a first stagein processing according to a second embodiment of the invention;

FIG. 5 is a cross section of the semiconductor structure of FIG. 4 at asubsequent stage in processing; and

FIG. 6 is a cross section of the semiconductor structure of FIG. 6 at asubsequent stage in processing.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In one aspect, transistors have enhanced carrier mobility by having thechannel region under both a uni-axial stress and a bi-axial stress. Theresult is that mobility is enhanced for both short and long channeltransistors and difference in mobility between the long channel andshort channel transistors is lessened. This is better understood byreference to the figures and the following description.

Shown in FIG. 1 is a semiconductor structure 10 comprising a aninsulating layer 12, a semiconductor layer 14 on insulating layer 12, atrench isolation 16 over insulating layer 12 and surroundingsemiconductor layer 14, a semiconductor layer 18 on semiconductor layer14, a gate dielectric 20, over a gate 22, a sidewall spacer 24 aroundgate 24, a source/drain extension region 23 on one side of gate 22, anda source/drain extension 25 on another side of gate 22. Semiconductorlayer 18 is epitaxially grown on semiconductor layer 14. Thussemiconductor layer 18 matches the crystalline structure and nearlymatches the crystal spacing of semiconductor layer 14. Due to the forcednear matching of the crystal spacing due to the epitaxial growth, thechange in material between semiconductor layers 14 and 18 causes astress change between the two. That the crystal spacing is different,albeit by a relatively small amount, between semiconductor layers 14 and18 does mean that there is a stress difference.

For the N channel case, semiconductor layer 14 is preferably silicon andsemiconductor layer 18 is preferably silicon carbide. The silicon ispreferably relaxed with the result that the silicon carbide is underbi-axial tensile stress. In the alternative, semiconductor layer 14 maybe at least partially relaxed silicon germanium and semiconductor layer18 can be either silicon or silicon carbide either which would be underbi-axial tensile stress.

For the P channel case, semiconductor layer 14 is preferably silicon andsemiconductor layer 18 is preferably silicon germanium. The silicon maybe relaxed with the result that the silicon germanium is under bi-axialcompressive stress. In the alternative, semiconductor layer 14 may beanother semiconductor material on which can be grown semiconductor layer18 to be under bi-axial compressive stress.

Shown in FIG. 2 is semiconductor structure 10 after etching source/drainextensions 23 and 25, semiconductor layer 18, and semiconductor layer14, to leave a recess 26 on the one side of gate 22 and a recess 28 onthe other side of gate 22.

Shown in FIG. 3 is semiconductor structure 10 after filling recesses 26and 28 with a semiconductor fill 30 and a semiconductor fill 32,respectively. Semiconductor fills 30 and 32 can be in situ doped ordoped by implant to become source/drain regions. The material forsemiconductor fills 30 and 32 is the same as the material type forsemiconductor layer 18 but may have a different ratio of the elementsthereof. For example, for the N channel case, the semiconductor materialmay be silicon carbide for the case in which semiconductor layer 18 issilicon carbide, but the ratio of silicon to carbon may be different.The silicon carbide case creates a uni-axial tensile stress insemiconductor layer 18. Similarly for the P channel case, semiconductorfills 30 and 32 may be silicon germanium for the case in whichsemiconductor layer is silicon germanium but the ratios of silicon togermanium may be different. The silicon germanium case creates auni-axial compressive stress in semiconductor layer 18. Semiconductorfills 30 and 32 are stressors that can provide either compressive ortensile stress, depending on the material, that is uni-axial.

The resulting semiconductor device 10 of FIG. 3 thus has a semiconductorregion 18 that is used as channel that is under both uni-axial stressand bi-axial stress. Thus mobility is enhanced for both long channel andshort channel. By adjusting the amount of stress of each type, themobility can be held much closer to being the same for both the long andshort channel cases.

Shown in FIG. 4 is a semiconductor structure 50 structure 50, comprisingan insulating layer 52, a semiconductor layer 54 of silicon germaniumthat is partially relaxed on insulating layer 52, a trench isolation 56surrounding semiconductor layer 54, a gate dielectric 62 onsemiconductor layer 54, a gate on gate dielectric 62, a sidewall spacer60 surrounding gate 58, a source/drain extension 64 in semiconductorlayer 54 on one side of gate 58, and a source/drain extension 66 insemiconductor layer 54 on another side of gate 58. This structure is fora P channel transistor because partially relaxed silicon germaniumprovides enhanced hole mobility due to its bi-axial compressive stress.

Shown in FIG. 5 is semiconductor structure 50 after etching throughsource/drain extensions 64 and 66 and into semiconductor layer 54, toleave a recess 68 on the one side of gate 58 and a recess 70 on theother side of gate 58.

Shown in FIG. 6 is semiconductor structure 50 after filling recesses 68and 70 with a semiconductor fill 72 and a semiconductor fill 74,respectively. The material for semiconductor fills 72 and 74 is the sameas the material type for semiconductor layer 54 but may have a differentratio of the elements thereof. Thus in this example in whichsemiconductor layer 54 is silicon germanium, the ratio of silicon togermanium in semiconductor fills 72 and 74 may be different than forsemiconductor layer 54. Semiconductor fills 72 and 74 can be in situdoped or doped by implant to become source/drain regions. In thissemiconductor device 50, semiconductor layer 54, as partially relaxedsilicon germanium, has a bi-axial compressive stress and further thereis applied an additional compressive stress that is uni-lateral throughthe formation of semiconductor fills 72 and 74. The result is a devicestructure that has both uni-axial and bi-axial stress. In this case, itis a compressive stress that is useful for P channel transistors, butwith different semiconductor materials it could be a tensile stress thatwould be useful for N channel transistors.

Shown in FIG. 7 is a semiconductor device 100 comprising an insulatinglayer 102, a semiconductor body 122 on insulating layer 102, asemiconductor body 104 on semiconductor body 122, a trench isolation 116surrounding semiconductor bodies 122 and 104, a gate dielectric 110 onsemiconductor body 104, a gate 106 on gate dielectric 110, a sidewallspacer 108 surrounding gate 106, a source/drain region 124 insemiconductor body 122 on one side of gate 106, a source/drain region126 in semiconductor body 122 on the other side of gate 106, asource/drain region 112 in semiconductor body 104 on the one side ofgate 106, a source/drain region 114 in semiconductor body 104 on theother side of gate 106, an insulator plug 118 spaced from gate 106 andthrough source/drain regions 112 and 124 to insulating layer 102, and aninsulator plug 120 spaced from gate 108 and through source/drain regions114 and 126.

For the P channel case, semiconductor layer 122 is preferably siliconand semiconductor layer 104 is preferably silicon germanium. The siliconmay be relaxed with the result that the silicon germanium is undercompressive stress. In the alternative, semiconductor layer 122 may beanother semiconductor material on which can be grown semiconductor layer104 to be under compressive stress.

Shown in FIG. 8 is a top view of semiconductor device 100 and showingwhere the cross section for FIG. 7 is taken. This shows insulator plug118 through source/drain region 112 and that there are plurality of suchinsulation plugs on the one side of gate 106 between gate 106 and trenchisolation 116. Similarly there is shown insulator plug 120 on the otherside of gate 106 and that there are a plurality of such insulator plugsthrough source/drain region 114. These isolation plugs, which arestressors, are formed at the same time and in the same way as trenchisolation 116. This is achieved by an oxide liner and an oxide, such asTEOS, fill. This semiconductor device 100 is an alternative approach forproviding a uni-axial stress. In this case the uni-axial stress is acompressive stress in semiconductor body 104.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present invention as set forthin the claims below. For example, a technique for obtaining uni-axialstress was described in FIGS. 1-6 but other alternatives may also beused such as that shown in FIGS. 7 and 8. Accordingly, the specificationand figures are to be regarded in an illustrative rather than arestrictive sense, and all such modifications are intended to beincluded within the scope of present invention.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

1-15. (canceled)
 16. A semiconductor device comprising: a substrate; asilicon layer formed over the substrate; a channel region formed overthe silicon layer, the channel region being bi-axially stressed; andsource and drain regions formed over the substrate, the source and drainregion providing uni-axial stress to the channel region.
 17. Thesemiconductor device of claim 16, wherein the substrate is asemiconductor substrate.
 18. The semiconductor device of claim 16,wherein the channel region comprises: a first layer comprising siliconformed on the substrate, the first layer having a first lattice spacing;and a second layer epitaxially grown on the first layer, the secondlayer comprising silicon and another element, the second layer having asecond lattice spacing that is larger than the first lattice spacing.19. The semiconductor device of claim 18, wherein the another element isgermanium.
 20. The semiconductor device of claim 16, wherein the channelregion comprises: a first layer comprising silicon formed over thesubstrate, the first layer having a first lattice spacing; and a secondlayer epitaxially grown on the first layer, the second layer comprisingsilicon and another element, the second layer having a second latticespacing that is smaller than the first lattice spacing.
 21. Thesemiconductor device of claim 20, wherein the another element is carbon.22. The semiconductor device of claim 16, wherein the semiconductordevice is a transistor having P-type conductivity.
 23. The semiconductordevice of claim 16, wherein the semiconductor device is a transistorhaving N-type conductivity.
 24. The semiconductor device of claim 16,wherein the channel region comprises: a bi-axially stressed layercomprising silicon and germanium formed over the substrate; a gate oxideformed over the bi-axially stressed layer; and a gate formed over thegate oxide.
 25. The semiconductor device of claim 16, wherein the sourceand drain regions comprises: a first layer comprising silicon formedover the substrate; source and drain extensions formed in the firstlayer, wherein a predetermined amount of the first layer is removed fromthe source and drain extensions to form source and drain recesses; afirst stressor formed in the source region; and a second stressor formedin the drain region, the first and second stressors comprising siliconand germanium, wherein the first and second stressors for providing theuni-axial stress to the channel region.
 26. The semiconductor device ofclaim 16, wherein the channel region comprises silicon and germanium andthe source and drain regions each comprise silicon and germanium,wherein a germanium content of the source and drain regions is higherthan a germanium content of the channel region.
 27. The semiconductordevice of claim 16 wherein the channel region comprises silicon andcarbon and the source and drain regions each comprise silicon andcarbon, wherein a carbon content of the source and drain regions ishigher than a carbon content of the channel region.
 28. Thesemiconductor device of claim 16, wherein both the bi-axial stress andthe uni-axial stress are tensile stress.
 29. The semiconductor device ofclaim 16, wherein both the bi-axial stress and the uni-axial stress arecompressive stress.